READY
Program loaded.
01 Program Program
Start at 00
Assembly listing
| Address | Machine code | Source instruction |
|---|
02 Processor CPU
ACC Calculator000
Z · 1N · 0
PC Next address00
IR Current instruction000
MAR Memory address00
MDR Memory data000
DECODEReady to fetch
PC → MAR → MDR → IR
Instructions completed0
Clock cycles0
CPU time0 μs
In-basket Input
Integers from 0–999, separated by spaces or commas. First in, first out.
Out-basket Output
Waiting for OUT
03 Mailboxes Memory
NextReadWriteDAT
Click a mailbox to inspect or edit its value and set a breakpoint. An orange dot marks a breakpoint.
04 Execution trace Register transfer language
Click “Step RTL” to follow each register transfer.
05Performance analysis
CPU time (μs) = clock cycles ÷ clock rate (MHz). Run speed only changes the animation; it does not change the simulated CPU clock.
Memory operations (reads + writes):
Counts reflect completed operations, including instruction fetches. Instruction counts update when an instruction finishes; the cycle total also includes a partially stepped instruction.
Lecture exercise: 3045 cycles
300 × 7 + 120 × 7 + 20 × 4 + 5 × 5 = 3045
At the selected clock rate:
| Instruction | Cycles each | Executed | Cycles |
|---|
Based on Lecture 5.1 (instruction set, examples and Von Neumann architecture) and Lecture 5.2 (RTL and performance). The negative-result display is a simulator convention; see Instructions & help. The LDA walkthrough separates decode as an explanation; the timing table uses 7 cycles for LDA.